View HYM322160GS-70_278760.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2M x 32-Bit Dynamic RAM Module
HYM 322160S/GS-60/-70
Advanced Information
* *
2 097 152 words by 32-Bit organization (alternative 4 194 304 words by 16-Bit) Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability with 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 4840 mW active (-60 version) max. 4400 mW active (-70 version) CMOS - 88 mW standby TTL - 176 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 8 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin double-sided Single in-Line Memory Module with 25.4 mm (1000 mil) height Utilizes sixteen 1M x 4 DRAMs in 300 mil SOJ packages 1024 refresh cycles / 16 ms Optimized for use in byte-write non-parity applications Tin-Lead contact pads (S- version) Gold contact pads (GS - version)
*
* *
*
* * * * * * * *
Semiconductor Group
1
9.94
HYM 322160S/GS-60/-70 2M x 32-Bit
The HYM322160S/GS-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by 32Bit in a 72-pin single-in-line package comprising sixteen HYB514400BJ 1M x 4 DRAMs in 300 mil wide SOJ-packages mounted together with eight 0.2 F ceramic decoupling capacitors on a PC board. The HYM322160S/GS-60/-70 can also be used as a 4 194 304 words by 16-Bits dynamic RAM module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, ..., DQ15 and DQ31, respectively. Each HYB514400BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 322160S/GS-60/-70 dictates the use of early write cycles. Ordering Information Type HYM 322160S-60 HYM 322160S-70 HYM 322160GS-60 HYM 322160GS-70 Ordering Code Q67100-Q2014 Q67100-Q2015 Q67100-Q2016 Q67100-Q2017 Package L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 L-SIM-72-11 Description DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns)
Semiconductor Group
2
HYM 322160S/GS-60/-70 2M x 32-Bit
Pin Configuration
Pin Names
VSS 1 DQ0 2 DQ16 3 DQ1 4 DQ17 5 DQ2 6 DQ18 7 DQ3 8 DQ19 9 VCC 10 N.C. 11 A0 12 A1 13 A2 14 A3 15 A4 16 A5 17 A6 18 N.C. 19 DQ4 20 DQ20 21 DQ5 22 DQ21 23 DQ6 24 DQ22 25 DQ7 26 DQ23 27 A7 28 N.C. 29 VCC 30 A8 31 A9 32 RAS3 33 RAS2 34 N.C. 35 N.C. 36 N.C. 37 VSS 39 CAS2 41 CAS1 43 RAS1 45 47 WE DQ8 49 DQ9 51 DQ10 53 DQ11 55 DQ12 57 VCC 59 DQ13 61 DQ14 63 DQ15 65 PD0 67 PD2 69 N.C. 71 N.C. 38 CAS0 40 CAS3 42 RAS0 44 N.C. 46 N.C. 48 DQ24 50 DQ25 52 DQ26 54 DQ27 56 DQ28 58 DQ29 60 DQ30 62 DQ31 64 N.C. 66 PD1 68 PD3 70 VSS 72
A0-A9 DQ0-DQ31 CAS0 - CAS3 RAS0 - RAS3 WE
Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -60 PD0 PD1 PD2 PD3 N.C. N.C. N.C. N.C. -70 N.C. N.C.
VSS
N.C.
Semiconductor Group
3
HYM 322160S/GS-60/-70 2M x 32-Bit
RAS0 CAS0 DQ0-DQ3 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D3
RAS1
CAS RAS I/O1-I/O4 OE D1 CAS RAS I/O1-I/O4 D2 OE
DQ4-DQ7 CAS1 DQ8-DQ11
CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D7 RAS3
CAS RAS I/O1-I/O4 OE D5 CAS RAS I/O1-I/O4 D6 OE
DQ12-DQ15
RAS2 CAS2 CAS RAS I/O1-I/O4 OE D8 CAS RAS I/O1-I/O4 OE D11
DQ16-DQ19
CAS RAS I/O1-I/O4 OE D9 CAS RAS I/O1-I/O4 D10 OE
DQ20-DQ23
CAS3 CAS RAS I/O1-I/O4 OE D12 CAS RAS I/O1-I/O4 D15 OE CAS RAS I/O1-I/O4 OE D13 CAS RAS I/O1-I/O4 D14 OE
DQ24-DQ27 DQ28-DQ31
A0-A9 WE
D0-D15 D0-D15
VCC VSS
C0 - C7
Block Diagram
Semiconductor Group
4
HYM 322160S/GS-60/-70 2M x 32-Bit
Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 6.2 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics1) TA = 0 to 70 C, VCC = 5 V 10 % Parameter Symbol Limit Values min. Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) max. 5.5 0.8 - 0.4 20 20 V V V V A A Unit Test Condition
VIH VIL VOH VOL II(L) IO(L)
2.4 - 1.0 2.4 - - 20 - 20
Average VCC supply current ICC1 (RAS, CAS, address cycling, tRC = tRC min) -60 version -70 version Standby VCC supply current (RAS = CAS = VIH)
- - -
880 800 32
mA mA mA
2)
,
3)
ICC2
Average VCC supply current ICC3 during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 version -70 version
- -
880 800
mA mA
2)
Semiconductor Group
5
HYM 322160S/GS-60/-70 2M x 32-Bit
DC Characteristics1) (cont'd) Parameter Symbol Limit Values min. max. Unit Test Condition
ICC4 Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -60 version -70 version
Standby VCC supply current (RAS = CAS = VCC - 0.2 V)
- - -
560 560 16
mA mA mA
2)
,
3)
ICC5
Average VCC supply current ICC6 during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 version -70 version
- -
880 800
mA mA
2)
Capacitance
TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz
Parameter Symbol Limit Values min. Input capacitance (A0 to A9, WE) Input capacitance (RAS0-RAS2, CAS0-CAS3) I/O capacitance (DQ0-DQ31) max. 120 40 29 pF pF pF Unit
CI1 CI2 CIO1
- - -
Semiconductor Group
6
HYM 322160S/GS-60/-70 2M x 32-Bit
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
M16F
Limit Values -50 min. max. - - 10k 10k - - - - 37 25 min. 110 40 60 15 0 10 0 15 20 15 15 60 - 50 16 5 3 - -60 max. - - 10k 10k - - - - 45 30 - - - 50 16
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM 322160S/GS-60/-70 2M x 32-Bit
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
M16F
Limit Values -50 min. max. - - - - - - - min. 10 10 0 15 15 0 10 -60 max. - - - - - - -
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 10 ns ns ns ns ns ns ns 14 14 13
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHCP 35 10 - 50 30 - - 30 200k - 40 10 - 60 35 - - 35 200k - ns ns ns ns ns 7
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Semiconductor Group
8
HYM 322160S/GS-60/-70 2M x 32-Bit
Notes:
1) All voltages are referenced to VSS . 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL . 6) Measured with a load equivalant of 2 TTL loads and 100 pF. 7) tOFF (max.) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance). 11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13)For CAS-before-RAS cycles only.
Semiconductor Group
9
HYM 322160S/GS-60/-70 2M x 32-Bit
Package Outline
GLS05834
Module Package, L-SIM-72-11 (Single in-Line Memory Module)
Semiconductor Group
10

▲Up To Search▲

Price & Availability of HYM322160GS-70

	To Download HYM322160GS-70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .